1. Field of the Invention
The present invention relates to a power supply circuit including a boosting circuit for boosting a power supply voltage and a semiconductor memory including the power supply circuit.
2. Background Art
Conventionally, for example, a semiconductor memory such as a NAND flash memory includes a power supply circuit for boosting a power supply voltage through a boosting circuit and supplying the power supply voltage.
For example, a semiconductor memory such as a NAND flash memory requires a higher potential than a power supply voltage because data is written, deleted, and read in the semiconductor memory. Thus such a semiconductor memory includes a boosting circuit for boosting a power supply voltage and a voltage detecting circuit for keeping the potential at a set potential.
In the boosting circuit, MOS transistors and capacitances are connected in series and one ends of the capacitances are connected via complementary CLK and CLKB signals to boost a power supply voltage.
The voltage detecting circuit includes a voltage dividing circuit and a comparator amplifier circuit. The output terminal of the boosting circuit and a ground potential are connected in series via the voltage dividing circuit. The comparator amplifier circuit compares a monitored potential outputted from the voltage dividing circuit with a reference potential.
As an example of the change of a detection level in the voltage detecting circuit, a plurality of n-type MOS transistors having ground potentials on the sources of the transistors are connected from the junction point of voltage dividing resistors of the voltage dividing circuit. A selecting signal is inputted to each of the gates of the transistors.
The selecting signal determines the set potential of the output of the boosting circuit. When the boosting circuit has an output lower than the set potential, the monitored potential is lower than the reference potential and the comparator amplifier circuit switches the output to, e.g., “High”. This output activates the boosting circuit and the output of the boosting circuit is boosted by a CLK/CLKB signals.
Conversely, when the boosting circuit has an output higher than the set potential, the monitored potential is higher than the reference potential and the comparator amplifier circuit switches the output to, e.g., “Low”. This output deactivates the boosting circuit and the CLK/CLKB signals are interrupted to stop the boosting operation of the boosting circuit.
As described above, the voltage detecting circuit activates and deactivates the boosting circuit, thereby keeping the output of the boosting circuit at around the set potential.
In the boosting operation, the output potential is not always kept at a fixed potential but fluctuates at around the set potential. This phenomenon is called ripples which increase or decrease with an RC time constant based on the resistance of the voltage dividing resistor, the operation delay of the comparator amplifier circuit, and the boosting capability of the boosting circuit. When the voltage dividing resistor has a large resistance, ripples increase with the operation delay of the comparator amplifier circuit and the boosting capability of the boosting circuit.
When the voltage dividing resistors have equal resistances and the same comparator amplifier circuit is used, the voltage detecting circuit has a constant rate of reaction relative to fluctuations in the potential of the boosting circuit. Therefore, time periods for switching the outputs of the voltage detecting circuit are substantially constant.
The output potential and the current of the boosting circuit have the following relationship: when the output potential of the boosting circuit is high, the output current is low. When the output potential of the boosting circuit is low, the output current is high.
Therefore, examining the output of the boosting circuit when the voltage detecting circuit has a low set potential, a current that can be outputted in a fixed time period increases and thus ripples increase.
On the other hand, when the voltage detecting circuit has a high set potential, a current that can be outputted in the fixed time period decreases and thus ripples decrease.
Furthermore, from another aspect, data is written in the cells of a NAND flash memory by the potential boosted by a boosting circuit.
However, the cell characteristics are not all uniform and the cells have different writing potentials enabling writing.
Thus the NAND flash memory is characterized in that the writing potential is gradually increased from a proper initial value and a writing operation is performed for each increase such that writing can be sequentially completed from a cell having a low potential enabling writing to a cell having a high potential enabling writing.
In order to achieve this operation, the voltage dividing resistors of the voltage detecting circuit for determining the set potential of the boosting circuit are adjusted to obtain a desired potential with a gradual increase from the output of the boosting circuit.
There is a problem that when the set potential is changed, as described above, the ripples of the output of the boosting circuit increase at a low set potential.
During a writing operation on cells of a NAND flash memory, when large ripples occur on the word lines of a selected cell and an unselected cell, for example, a Vth distribution of written cells expands and writing is erroneously performed on the unselected cell. Therefore, small ripples are more desirable. If further multiple values are stored in memory cells in the future, it would be strongly desired to suppress the expansion of a Vth distribution.
However, as described above, during a writing operation on a cell having a low potential enabling writing, when the voltage dividing resistors of the voltage detecting circuit are adjusted to set a low output of the boosting circuit, the conventional circuit has large ripples and deteriorates the characteristics of writing on memory cells.
In this conventional power supply circuit, the voltage detecting circuit has two detection levels and the boosting circuit performs a boosting operation with normal boosting capability until a low first detection level. In some power supply circuits, when exceeding the first detection level, the frequency of an input clock signal is reduced and the boosting capability is degraded to activate or deactivate the boosting circuit at around a higher second detection level (for example, see Japanese Patent Laid-Open No. 2005-190533).
Although ripples can be reduced at around a set potential in this conventional power supply circuit, the dependence of ripples on the set potential is not reduced.